MIPS_EXT(5)MIPS_EXT(5) NAME mips_ext - MIPS architecture extensions and the -mipsn compiler option DESCRIPTION This man page describes the -mipsn option to the cc, f77, and f90 command line. n can be 2, 3, or 4. Each type of extension is described here. The MIPS 2 Extension The MIPS R4000 processor contains many instruction set extensions to the MIPS1 instruction set that was defined by the MIPS R2000/R3000. A subset of these instruction set extensions defines the MIPS2 instruction set and is accessible with the -mips2 option. This extension instructs the code generation phase of the compiler to generate the MIPS2 instructions wherever beneficial. The option also causes the instruction scheduler phase to use the R4000 processor model while scheduling instructions. When linking, the -mips2 option instructs the linker, ld(1), to use MIPS2-specific versions of libraries from the /usr/lib/mips2 directory. The following features are added by the MIPS2 instruction set extensions: * Double precision floating-point load and store instructions. This can provide significant improvement to code using double precision floating-point manipulation. A single instruction can load/store a double precision floating-point value. In contrast, the R2000/R3000 required using two instructions to reference the upper half and the lower half of the double precision value. * Intrinsic instructions to convert floating-point numbers. The instructions provide truncate, round, ceiling and floor operations. On the R2000/R3000, these instructions were implemented as assembler macros which expanded into approximately 11 instructions. Code which does a significant amount of floating-point to integer conversions benefits from the -mips2 option. * Floating point SQRT instruction. This is faster than the SQRT routine in the math libraries for the R2000/R3000. * Branch-likely instructions. Every branch instruction in the MIPS1 architecture has a corresponding branch-likely form. In this form of the branch, the instruction in the delay slot of the branch is nullified if the conditional branch is not taken. * New compare and trap instructions, which cause an exception to be raised based on the result of comparing two registers or a register and immediate value. In the R2000/R3000, these instructions were implemented as assembler macros which expanded into a sequence using a conditional branch and a break instruction. A special set of libraries compiled with the -mips2 option and making use of MIPS2 features is provided in the /usr/lib/mips2 directory. MIPS2 versions of libfastm.a, libm.a and libm43.a libraries are provided as part of the basic development environment. MIPS2 versions of libF77.a, libI77.a, libU77.a and libisam are provided as part of the Fortran compiler. The shared library versions of these Fortran libraries do not currently have a MIPS2 version. Code compiled and/or linked using the -mips2 option does not run on R2000/R3000 based machines. Code compiled without the -mips2 option runs on all machines - R2000/R3000/R4000 - within the constraints of operating system compatibility. If broad machine base compatibility is an issue, use the -mips2 option only when significant benefit is achieved on an R4000 based system as compared to running the same program compiled without the -mips2 option on the same R4000 based system. The double precision floating-point load and store instructions require the data to be aligned on a double word boundary. A non- aligned access causes the program to abort with a bus error message. This requirement may cause some programs to fail when recompiled with the -mips2 option. This can happen in some Fortran programs that have common blocks with an odd number of integer values followed by double precision data. The MIPS3 Extension The MIPS3 extensions were introduced in the R4000 processors and primarily support 64-bit addresses and arithmetic and a larger floating-point register set. The 64-bit addressing features are only supported on machines running a 64-bit kernel. The 64-bit arithmetic features are supported on all machines running IRIX 6.2 and later releases (R4000 and later CPUs). The MIPS3 instruction set extensions provide the following features: * 64-bit integer registers, with a complete set of instructions to perform 64-bit integer arithmetic operations. * 64-bit addresses and pointers. The R4000 family and later MIPS processors support a 64-bit flat address space. * Thirty-two 64-bit floating-point registers. The R4000 family supports two floating-point register (FPR) modes, determining how many 64-bit FPRs are available: 16-FPR mode and 32-FPR mode. The 16-FPR mode is compatible with the R2000/R3000 and is available using the default (-mips1) or -mips2 compiler options. The 32-FPR mode is not compatible with the MIPS1 or MIPS2 model. Therefore, it is only supported by the -mips3 and -mips4 options. The SGI Pascal compiler, pc, does not support the -mips3 option or the MIPS3 instruction set. The MIPS4 Extension The MIPS4 instruction set extensions consist of a backward compatible superset of the MIPS3 instruction set. The MIPS4 extensions are intended primarily to provide better performance in floating-point numeric processing. These features are currently supported under IRIX 6.2 and later releases running on machines with the R8000, R10000, or R5000 microprocessors. The MIPS4 instruction set extensions provide the following features: * A new set of multiply-add instructions takes advantage of the fact that the majority of floating-point computations use the chained multiply-add paradigm. These instructions have lower inherent latency (temporary result need not be written back to a register) and higher performance (fewer instructions to fetch and decode). The multiple-add instructions on an R8000 (but not on R5000 or R10000) does not perform intermediate rounding, for even lower latency. * A register+register addressing mode for floating-point loads and stores eliminates the extra integer add required in many array accesses. (Register+register addressing for integer memory operations is not supported.) * A set of four conditional move operators allows some simple IF statements to be represented without branches. THEN and ELSE clauses are computed unconditionally and the results placed in a temporary register. Conditional move operators then select the correct temporary result. * Memory prefetch instructions to better manage data cache behavior in memory intensive algorithms. Prefetch instructions are not supported on the R8000. See mipscheck(1) for details. NOTES Programs compiled with the -mips3 or -mips4 option conform to the MIPS 64-bit application binary interface (ABI64) or n32 ABI (ABIn32), rather than the original MIPS ABI (ABIo32). Each of the 3 ABIs is distinct and object files compiled to one ABI cannot be linked to object files (including archives and DSOs) compiled to another ABI. SEE ALSO Assembly Language Programmer's Guide. MIPSpro 64-Bit Porting and Transition Guide MIPSpro N32 ABI Handbook MIPS RISC Architecture, Gerry Kane and Joe Heinrich, Prentice Hall. MIPS R4000 User's Manual, Joseph Heinrich, Prentice Hall. as(1), cc(1), CC(1), f77(1), pc(1)