MAKE(1) MAKE(1) NAME make - maintain, update, and regenerate groups of programs (DEVELOPMENT) SYNOPSIS make [-eiknpqrsStuwdDPBNMOg] [-f makefile] ... [macros=name] ... [target_name] ... DESCRIPTION The make utility can be used as a part of software development to update files that are derived from other files. A typical case is one where object files are derived from the corresponding source files. The make utility examines time relationships and updates those derived files (called targets) that have modified times earlier than the modified times of the files (called prerequisites) from which they are derived. A description file (makefile) contains a description of the relationships between files, and the commands that must be executed to update the targets to reflect changes in their prerequisites. Each specification, or rule, consists of a target, optional prerequisites and optional commands to be executed when a prerequisite is newer than the target. There are two types of rule: - inference rules, which have one target name with at least one period (.) and no slash (/) - target rules, which can have more than one target name. In addition, make has a collection of built-in macros and inference rules that infer prerequisite relationships to simplify maintenance of programs. To receive exactly the behaviour described in this section, a portable makefile must: - include the special target .POSIX - omit any special target reserved for implementations (a leading period followed by upper-case letters) that has not been specified by this section. NOTE: See COMPATIBILITY ISSUES section below for when these conditions are not met. OPTIONS The following options are supported: -b Compatibility mode for old makefiles. -B Blocked output. In parallel mode, the output from concurrently updating targets can be either intermingled or saved up and printed upon completion of the target. The default is to intermingle the output, this option turns on the 'blocking' of output until the target has completed. -d Debug. As targets are traversed, the reason they are being updated is printed. -D Debug. A full dump of all aspects of target and variable handling. This option usually produces an overwhelming amount of information. -e Cause environment variables, including those with null values, to override macro assignments within makefiles. -f makefile Specify a different makefile. The argument makefile is a pathname of a description file, which is also referred to as the makefile. A pathname of - denotes the standard input. There can be multiple instances of this option, and they will be processed in the order specified. -g Auto get. If a file does not exist, attempt to 'get' it from SCCS using the $(GET) macro. -i Ignore error codes returned by invoked commands. This mode is the same as if the special target .IGNORE were specified without prerequisites. -k Continue to update other targets that do not depend on the current target if a non-ignored error occurs while executing the commands to bring a target up-to-date. -M Turn off -N (this is the default). -n Write commands that would be executed on standard output, but do not execute them. However, lines with a plus sign (+) prefix will be executed. In this mode, lines with an at sign (@) character prefix will be written to standard output. -N Permit targets that have dependencies to still be candidates for application of the empty rule (NULL) suffix transformation rules (see the "Inference Rules" section below). -O Turn off compatibility mode for old makefiles. -p Write to standard output the complete set of macro definitions and target descriptions. The output format is unspecified. -P Parallel. Enables building independent parts of the makefile concurrently (see "Parallel Execution" section below). -q Return a zero exit value if the target file is up-to-date; otherwise, return an exit value of 1 (one). Targets will not be updated if this option is specified. However, a command line (associated with the targets) with a plus sign (+) prefix will be executed. -r Clear the suffix list and do not use the built-in rules. -s Do not write command lines or touch messages (see -t) to standard output before executing. This mode is the same as if the special target .SILENT were specified without prerequisites. -S Terminate make if an error occurs while executing the commands to bring a target up-to-date. This will be the default and the opposite of the -k option. -t Update the modification time of each target as though a touch target had been executed. Targets that have prerequisites but no commands (see Target Rules), or that are already up-to-date, will not be touched in this manner. Write messages to standard output for each target file indicating the name of the file and that it was touched. Normally, the command lines associated with each target are not executed. However, a command line with a plus sign (+) prefix will be executed. -u Unconditional. Build all targets regardless of whether they are up-to-date or not. -w Suppress warning messages. Fatal messages will not be affected. If the -k and -S options are both specified on the command line, by the MAKEFLAGS environment variable, or by the MAKEFLAGS macro, the last one evaluated will take precedence. The MAKEFLAGS environment variable will be evaluated first and the command line will be evaluated second. Assignments to the MAKEFLAGS macro will be evaluated as described in the "ENVIRONMENT VARIABLES" section. OPERANDS The following operands are supported: target_name Target names, as defined in EXTENDED DESCRIPTION. If no target is specified, while make is processing the makefiles, the first target that make encounters that is not a special target or an inference rule will be used. macro=name Macro definitions, as defined in the Macros section. STDIN The standard input will be used only if the makefile option-argument is -. See INPUT FILES section. INPUT FILES The input file, otherwise known as the makefile, is a text file containing rules, macro definitions and comments. ENVIRONMENT VARIABLES The following environment variables affect the execution of make: MAKEFLAGS This variable is interpreted as a character string representing a series of option characters to be used as the default options. The implementation will accept both of the following formats (but need not accept them when intermixed): 1. The characters are option letters without the leading hyphens or blank character separation used on a command line. 2. The characters are formatted in a manner similar to a portion of the make command line: options are preceded by hyphens and blank-character-separated. The macro=name macro definition operands can also be included. The difference between the contents of MAKEFLAGS and the command line is that the contents of the variable will not be subjected to the word expansions. When the command-line options -f or -p are used, they will take effect regardless of whether they also appear in MAKEFLAGS. The MAKEFLAGS variable will be accessed from the environment before the makefile is read. At that time, all of the options (except -f and -p ) and command-line macros not already included in MAKEFLAGS are added to the MAKEFLAGS macro. The MAKEFLAGS macro will be passed into the environment as an environment variable for all child processes. If the MAKEFLAGS macro is subsequently set by the makefile, it replaces the MAKEFLAGS variable currently found in the environment. The value of the SHELL environment variable will not be used as a macro and will not be modified by defining the SHELL macro in a makefile or on the command line. All other environment variables, including those with null values, are used as macros, as defined in the "Macros" section. ASYNCHRONOUS EVENTS If not already ignored, make will trap SIGHUP, SIGTERM, SIGINT and SIGQUIT and remove the current target unless the target is a directory or the target is a prerequisite of the special target .PRECIOUS or unless one of the -n, -p or -q options was specified. Any targets removed in this manner will be reported in diagnostic messages of unspecified format, written to standard error. After this cleanup process, if any, make will take the standard action for all other signals. STDOUT The make utility will write all commands to be executed to standard output unless the s option was specified, the command is prefixed with an at sign, or the special target .SILENT has either the current target as a prerequisite or has no prerequisites. If make is invoked without any work needing to be done, it will write a message to standard output indicating that no action was taken. STDERR Used only for diagnostic messages. OUTPUT FILES None. However, utilities invoked by make may create additional files. EXTENDED DESCRIPTION The make utility attempts to perform the actions required to ensure that the specified targets are up-to-date. A target is considered out-of-date if it is older than any of its prerequisites or if it does not exist. The make utility treats all prerequisites as targets themselves and recursively ensures that they are up-to-date, processing them in the order in which they appear in the rule. The make utility uses the modification times of files to determine if the corresponding targets are out-of-date. After make has ensured that all of the prerequisites of a target are up- to-date and if the target is out-of-date, the commands associated with the target entry are executed. If there are no commands listed for the target, the target is treated as up-to-date. Makefile Syntax A makefile can contain rules, macro definitions, and comments. There are two kinds of rules: inference rules and target rules. The make utility contains a set of built-in inference rules. If the -r option is present, the built-in rules are not used and the suffix list is cleared. Additional rules of both types can be specified in a makefile. If a rule or macro is defined more than once, the value of the rule or macro will be that of the last one specified. Comments start with a number sign (#) and continue until an unescaped newline character is reached. By default, the following files are tried in sequence: ./makefile, ./Makefile, ./s.makefile, SCCS/s.makefile, ./s.Makefile and SCCS/s.Makefile. The -f option directs make to ignore any of these default files and use the specified argument as a makefile instead. If the - argument is specified, standard input will be used. The term makefile is used to refer to any rules provided by the user, whether in The rules in makefiles consist of the following types of lines: target rules, including special targets (see Target Rules); inference rules (see Inference Rules); macro definitions (see Macros); empty lines; and comments. Comments start with a number sign (#) and continue until an unescaped newline character is reached. When an escaped newline character (one preceded by a backslash) is found anywhere in the makefile, it is replaced, along with any leading white space on the following line, with a single space character. Makefile Execution Command lines are processed one at a time by writing the command line to the standard output (unless one of the conditions listed below under @ suppresses the writing) and executing the commands in the line. A tab character may precede the command to standard output. Commands will be executed by passing the command line to the command interpreter in the same manner as if the string were the argument to the system() function. The environment for the command being executed will contain all of the variables in the environment of make. The macros from the command line to make will be added to make's environment. Other implementation-dependent variables may also be added to make's environment. If any command-line macro has been defined elsewhere, the command-line value will overwrite the existing value. If the MAKEFLAGS variable is not set in the environment in which make was invoked, in the makefile or on the command line, it will be created by make, and will contain all options specified on the command line except for the -f and -p options. It may also contain implementation-dependent options. By default, when make receives a non-zero status from the execution of a command, it terminates with an error message to standard error. Command lines can have one or more of the following prefixes: a hyphen (-), an at sign (@), or a plus sign (+). These modify the way in which make processes the command. When a command is written to standard output, the prefix is not included in the output. - If the command prefix contains a hyphen, or the -i option is present, or the special target .IGNORE has either the current target as a prerequisite or has no prerequisites, any error found while executing the command will be ignored. @ If the command prefix contains an at sign and the command-line n option is not specified, or the s option is present, or the special target .SILENT has either the current target as a prerequisite or has no prerequisites, the command will not be written to standard output before it is executed. + If the command prefix contains a plus sign, this indicates a command line that will be executed even if -n, -q or -t is specified. Include Files If the string include or sinclude appears at the beginning of a line in a makefile, and is followed by a blank or a tab, the rest of the line is assumed to be a filename and will be read by the current invocation, after substituting for any macros. For include it is a fatal error if the file is not readable, for sinclude a non-readable file is silently ignored. Alternate Make make understands a convention similar to the alternate interpreter feature of exec(2) . If the first line of the makefile starts with a #!alternate_make , then make will attempt to exec the alternate make with the same environment and arguments that make itself was invoked with. Additional arguments may be supplied on the #! line - these are placed ahead of all the command line arguments given to the original invocation of make . If a new makefile specification is given using the -f flag, any original -f options given on the command line are ignored. If the alternate make cannot be found in the user's PATH or make finds that it would be re-invoking itself, then make silently ignores the line and continues to execute the remainder of the makefile. The -d flag will display information as to whether the alternate make was successfully invoked. As a special case to support compatibility with a makefile used as a shell script (with a "#!/bin/make -f"), a lone -f flag is ignored. Parallel Execution The -P option turns on parallel execution. In this mode make views all dependencies for a given target as independent, and works on a set of them concurrently. By default, the concurrency factor is two. This may be changed by setting the environment variable PARALLEL. Note that some makefiles make use of the property that in the non-parallel versions of make dependencies were brought up to date in the order listed. The following makefile relies on this ordering and thus would not work correctly when invoked with the parallel option: default: a b a: mkdir foo b: cd foo; echo hi Target Rules Target rules are formatted as follows: target [target...]: [prerequisite...][; command ] [<tab> command <tab> command ...] line that does not begin with <tab> Target entries are specified by a blank-character-separated, non-null list of targets, then a colon, then a blank-character-separated, possibly empty list of prerequisites. Text following a semicolon, if any, and all following lines that begin with a tab character, are command lines to be executed to update the target. The first non-empty line that does not begin with a tab character or # begins a new entry. An empty or blank line, or a line beginning with #, may begin a new entry. Applications must select target names from the set of characters consisting solely of periods, underscores, digits and alphabetics from the portable character set. Implementations may allow other characters in target names as extensions. The interpretation of targets containing the characters (%) and (") is implementation-dependent. A target that has prerequisites, but does not have any commands, can be used to add to the prerequisite list for that target. Only one target rule for any given target can contain commands. Lines that begin with one of the following are called special targets and control the operation of make: .DEFAULT If the makefile uses this special target, it must be specified with commands, but without prerequisites. The commands will be used by make if there are no other rules available to build a target. .IGNORE Prerequisites of this special target are targets themselves; this will cause errors from commands associated with them to be ignored in the same manner as specified by the -i option. Subsequent occurrences of .IGNORE add to the list of targets ignoring command errors. If no prerequisites are specified, make will behave as if the -i option had been specified and errors from all commands associated with all targets will be ignored. .MAKEOPTS Any command line option except -[ref] may be set in a makefile by listing it as a dependency to this target. Note that this is a target not a macro; do not assign (using an '=') a value to it. .POSIX This special target must be specified without prerequisites or commands. If it appears before the first non-comment line in the makefile, make will process the makefile as specified by this section; otherwise, the behaviour of make is unspecified. .PRECIOUS Prerequisites of this special target will not be removed if make receives one of the asynchronous events explicitly described in ASYNCHRONOUS EVENTS. Subsequent occurrences of .PRECIOUS add to the list of precious files. If no prerequisites are specified, all targets in the makefile will be treated as if specified with .PRECIOUS. .SCCS_GET This special target must be specified without prerequisites. If this special target is included in a makefile, the commands specified with this target replace the default commands associated with this special target. (See "Default Rules"). The commands specified with this target are used to get all SCCS files that are not found in the current directory. When source files are named in a dependency list, make treats them just like any other target. Because the source file is presumed to be present in the directory, there is no need to add an entry for it to the makefile. When a target has no dependencies, but is present in the directory, make assumes that that file is up-to-date. If, however, an SCCS file named SCCS/s.source_file is found for a target source_file, make does some additional checking to assure that the target is up-to-date. If the target is missing, or if the SCCS file is newer, make automatically issues the commands specified for the .SCCS_GET special target to retrieve the most recent version. However, if the target is writable by anyone, make does not retrieve a new version. .SILENT Prerequisites of this special target are targets themselves; this causes commands associated with them to not be written to the standard output before they are executed. Subsequent occurrences of .SILENT add to the list of targets with silent commands. If no prerequisites are specified, make will behave as if the -s option had been specified and no commands or touch messages associated with any target will be written to standard output. .SUFFIXES Prerequisites of .SUFFIXES are appended to the list of known suffixes and are used in conjunction with the inference rules (see "Inference Rules" ). If .SUFFIXES does not have any prerequisites, the list of known suffixes will be cleared. Makefiles must not associate commands with .SUFFIXES. Targets with names consisting of a leading period followed by the upper-case letters POSIX and then any other characters are reserved for future standardisation. Targets with names consisting of a leading period followed by one or more upper-case letters are reserved for implementation extensions. Macros Macro definitions are in the form: string1 = [ string2 ] The macro named string1 is defined as having the value of string2, where string2 is defined as all characters, if any, after the equal sign, up to a comment character (#) or an unescaped newline character. Any blank characters immediately before or after the equal sign will be ignored. Subsequent appearances of $(string1) or ${string1} are replaced by string2. The parentheses or braces are optional if string1 is a single character. The macro $$ is replaced by the single character $ in effect escaping the $ character. See NOTES below about macros defined within macros. Applications must select macro names from the set of characters consisting solely of periods, underscores, digits and alphabetics from the portable character set. A macro name cannot contain an equal sign. Implementations may allow other characters in macro names as extensions. Macros can appear anywhere in the makefile. Macros in target lines will be evaluated when the target line is read. Macros in command lines will be evaluated when the command is executed. Macros in macro definition lines will not be evaluated until the new macro being defined is used in a rule or command. A macro that has not been defined will evaluate to a null string without causing any error condition. The forms $(string1[:subst1=[subst2]]) or ${string1[:subst1=[subst2]]} can be used to replace all occurrences of subst1 with subst2 when the macro substitution is performed. The subst1 to be replaced is recognised when it is a suffix at the end of a word in string1 (where a word, in this context, is defined to be a string delimited by the beginning of the line, a blank or newline character). Macro assignments will be accepted from the sources listed below, in the order shown. If a macro name already exists at the time it is being processed, the newer definition will replace the existing definition. 1. Macros defined in make's built-in inference rules. 2. The contents of the environment, including the variables with null values, in the order defined in the environment. 3. Macros defined in the makefiles, processed in the order specified. 4. Macros specified on the command line. It is unspecified whether the internal macros defined in Internal Macros are accepted from the command line. If the -e option is specified, the order of processing sources items 2 and 3 will be reversed. The SHELL macro is treated specially. It is provided by make and set to the pathname of the shell command language interpreter (see The SHELL environment variable will not affect the value of the SHELL macro. If SHELL is defined in the makefile or is specified on the command line, it will replace the original value of the SHELL macro, but will not affect the SHELL environment variable. Other effects of defining SHELL in the makefile or on the command line are implementation-dependent. Inference Rules Inference rules are formatted as follows: target: <tab>command [<tab>command ] ... line that does not begin with <tab> or # The target portion must be a valid target name (see "Target Rules") of the form .s2 or .s1.s2 (where .s1 and .s2 are suffixes that have been given as prerequisites of the .SUFFIXES special target and s1 and s2 do not contain any slashes or periods.) If there is only one period in the target, it is a single-suffix inference rule. Targets with two periods are double-suffix inference rules. Inference rules can have only one target before the colon. The makefile must not specify prerequisites for inference rules; no characters other than white space can follow the colon in the first line, except when creating the empty rule, described below. Prerequisites are inferred, as described below. Inference rules can be redefined. A target that matches an existing inference rule will overwrite the old inference rule. An empty rule can be created with a command consisting of simply a semicolon (that is, the rule still exists and is found during inference rule search, but since it is empty, execution has no effect). The empty rule also can be formatted as follows: rule: ; where zero or more blank characters separate the colon and semicolon. The make utility uses the suffixes of targets and their prerequisites to infer how a target can be made up-to-date. A list of inference rules defines the commands to be executed. By default, make contains a built-in set of inference rules. Additional rules can be specified in the makefile. The special target .SUFFIXES contains as its prerequisites a list of suffixes that are to be used by the inference rules. The order in which the suffixes are specified defines the order in which the inference rules for the suffixes are used. New suffixes will be appended to the current list by specifying a .SUFFIXES special target in the makefile. A .SUFFIXES target with no prerequisites will clear the list of suffixes. An empty .SUFFIXES target followed by a new .SUFFIXES list is required to change the order of the suffixes. Normally, the user would provide an inference rule for each suffix. The inference rule to update a target with a suffix .s1 from a prerequisite with a suffix .s2 is specified as a target .s2.s1. The internal macros provide the means to specify general inference rules. (See Internal Macros) When no target rule is found to update a target, the inference rules are checked. The suffix of the target (.s1) to be built is compared to the list of suffixes specified by the .s1 suffix is found in .SUFFIXES, the inference rules are searched in the order defined for the first .s2.s1 rule whose prerequisite file ($*.s2) exists. If the target is out-of-date with respect to this prerequisite, the commands for that inference rule are executed. If the target to be built does not contain a suffix and there is no rule for the target, the single suffix inference rules will be checked. The single-suffix inference rules define how to build a target if a file is found with a name that matches the target name with one of the single suffixes appended. A rule with one suffix .s2 is the definition of how to build target from target.s2. The other suffix (.s1) is treated as null. A tilde (~) in the above rules refers to an SCCS file in the current directory. Thus, the rule .c.o would transform an SCCS C-language source file into an object file (.o). Because the s. of the SCCS files is a prefix, it is incompatible with make's suffix point of view. Hence, the ~ is a way of changing any file reference into an SCCS file reference. Libraries If a target or prerequisite contains parentheses, it will be treated as a member of an archive library. For the lib(member.o) expression lib refers to the name of the archive library and member.o to the member name. The member must be an object file with the .o suffix. The modification time of the expression is the modification time for the member as kept in the archive library (See ar). The .a suffix refers to an archive library. The .s2.a rule is used to update a member in the library from a file with a suffix .s2. Internal Macros The make utility maintains five internal macros that can be used in target and inference rules. In order to clearly define the meaning of these macros, some clarification of the terms target rule, inference rule, target and prerequisite is necessary. Target rules are specified by the user in a makefile for a particular target. Inference rules are user- or make -specified rules for a particular class of target names. Explicit prerequisites are those prerequisites specified in a makefile on target lines. Implicit prerequisites are those prerequisites that are generated when inference rules are used. Inference rules are applied to implicit prerequisites or to explicit prerequisites that do not have target rules defined for them in the makefile. Target rules are applied to targets specified in the makefile. Before any target in the makefile is updated, each of its prerequisites (both explicit and implicit) will be updated. This is accomplished by recursively processing each prerequisite. Upon recursion, each prerequisite becomes a target itself. Its prerequisites in turn are processed recursively until a target is found that has no prerequisites, at which point the recursion stops. The recursion then backs up, updating each target as it goes. In the definitions that follow, the word target refers to one of: - a target specified in the makefile - an explicit prerequisite specified in the makefile that becomes the target when make processes it during recursion - an implicit prerequisite that becomes a target when make processes it during recursion. In the definitions that follow, the word prerequisite refers to one of the following: - an explicit prerequisite specified in the makefile for a particular target - an implicit prerequisite generated as a result of locating an appropriate inference rule and corresponding file that matches the suffix of the target. The internal macros are: $@ The $@ evaluates to the full target name of the current target, or the archive filename part of a library archive target. It is evaluated for both target and inference rules. For example, in the .c.a inference rule, $@ represents the out-of-date .a file to be built. Similarly, in a makefile target rule to build lib.a from file.c, $@ represents the out-of-date lib.a. $$@ The $$@ macro stands for the full target name of the current target (which is $@). It has meaning only on the dependency line in a makefile. Thus, in the following: cat dd: $$@.c the dependency is translated at execution time first to the string cat.c, then to the string dd.c. $% The $% macro is evaluated only when the current target is an archive library member of the form libname(member.o). In these cases, $@ evaluates to libname and $% evaluates to member.o. The $% macro is evaluated for both target and inference rules. For example, in a makefile target rule to build lib.a(file.o), $% represents file.o as opposed to $@, which represents lib.a. $? The $? macro evaluates to the list of prerequisites that are newer than the current target. It is evaluated for both target and inference rules. For example, in a makefile target rule to build prog from file1.o, file2.o and file3.o, and where prog is not out of date with respect to file1.o, but is out of date with respect to file2.o and file3.o, $? represents file2.o and file3.o. $< In an inference rule, $< evaluates to the file name whose existence allowed the inference rule to be chosen for the target. In the .DEFAULT rule, the $< macro evaluates to the current target name. The $< macro is evaluated only for inference rules. For example, in the .c.a inference rule, $< represents the prerequisite .c file. $* The $* macro evaluates to the current target name with its suffix deleted. It is evaluated at least for inference rules. For example, in the .c.a inference rule, $*.o represents the out-of-date .o file that corresponds to the prerequisite .c file. Each of the internal macros has an alternative form. When an upper-case D or F is appended to any of the macros, the meaning is changed to the directory part for D and filename part for F. The directory part is the path prefix of the file without a trailing slash; for the current directory, the directory part is ``.''. When the $? macro contains more than one prerequisite filename, the $(?D) and $(?F) (or ${?D} and ${?F}) macros expand to a list of directory name parts and filename parts respectively. For the target lib(member.o) and the s2.a rule, the internal macros are defined as: $< member.s2 $* member $@ lib $? member.s2 $% member.o Default Rules The default rules for make achieve results that are the same as if the following were used. SPECIAL TARGETS: .SCCS_GET: sccs $(SCCSFLAGS) get $(SCCSGETFLAGS) $@ .SUFFIXES: .o .c .y l .a .sh .f .c~ .y~ .l~ .sh~ .f~ MACROS: MAKE=make AR=ar ARFLAGS=-rv YACC=yacc YFLAGS= LEX=lex LFLAGS= LDFLAGS= CC=c89 CFLAGS=-O FC=fort77 FFLAGS=-O 1 GET=get GFLAGS= SCCSFLAGS= SCCSGETFLAGS=-s SINGLE SUFFIX RULES .c: $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< .f: $(FC) $(FFLAGS) $(LDFLAGS) -o $@ $< .sh: cp $< $@ chmod a+x $@ .c~: $(GET) $(GFLAGS) -p $< > $*.c $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $*.c .f~: $(GET) $(GFLAGS) -p $< > $*.f $(FC) $(FFLAGS) $(LDFLAGS) -o $@ $*.f .sh~: $(GET) $(GFLAGS) -p $< > $*.sh cp $*.sh $@ chmod a+x $@ DOUBLE SUFFIX RULES .c.o: $(CC) $(CFLAGS) -c $< .f.o: $(FC) $(FFLAGS) -c $< .y.o: $(YACC) $(YFLAGS) $< $(CC) $(CFLAGS) -c y.tab.c rm -f y.tab.c mv y.tab.o $@ .l.o: $(LEX) $(LFLAGS) $< $(CC) $(CFLAGS) -c lex.yy.c rm -f lex.yy.c mv lex.yy.o $@ .y.c: $(YACC) $(YFLAGS) $< mv y.tab.c $@ .l.c: $(LEX) $(LFLAGS) $< mv lex.yy.c $@ .c~.o: $(GET) $(GFLAGS) -p $< > $*.c $(CC) $(CFLAGS) -c $*.c .f~.o: $(GET) $(GFLAGS) -p $< > $*.f $(FC) $(FFLAGS) -c $*.f .y~.o: $(GET) $(GFLAGS) -p $< > $*.y $(YACC) $(YFLAGS) $*.y $(CC) $(CFLAGS) -c y.tab.c rm -f y.tab.c mv y.tab.o $@ .l~.o: $(GET) $(GFLAGS) -p $< > $*.l $(LEX) $(LFLAGS) $*.l $(CC) $(CFLAGS) -c lex.yy.c rm -f lex.yy.c mv lex.yy.o $@ .y~.c: $(GET) $(GFLAGS) -p $< > $*.y $(YACC) $(YFLAGS) $*.y mv y.tab.c $@ .l~.c: $(GET) $(GFLAGS) -p $< > $*.l $(LEX) $(LFLAGS) $*.l mv lex.yy.c $@ .c.a: $(CC) -c $(CFLAGS) $< $(AR) $(ARFLAGS) $@ $*.o rm -f $*.o .f.a: $(FC) -c $(FFLAGS) $< $(AR) $(ARFLAGS) $@ $*.o rm -f $*.o EXIT STATUS When the -q option is specified, the make utility will exit with one of the following values: 0 Successful completion. 1 The target was not up-to-date. >1 An error occurred. When the -q option is not specified, the make utility will exit with one of the following values: 0 successful completion >0 an error occurred APPLICATION USAGE If there is a source file (such as ./source.c) and there are two SCCS files corresponding to it (./s.source.c and ./SCCS/s.source.c), make will use the SCCS file in the current directory. However, users are advised to use the underlying SCCS utilities (admin, delta, get, and so forth) or the sccs utility for all source files in a given directory. If both forms are used for a given source file, future developers may be confused. It is incumbent upon portable makefiles to specify the .POSIX special target in order to guarantee that they are not affected by local extensions. The -k and -S options are both present so that the relationship between the command line, the MAKEFLAGS variable, and the makefile can be controlled precisely. If the -k flag is passed in MAKEFLAGS and a command is of the form: $(MAKE) -S foo then the default behaviour is restored for the child make. When the -n option is specified, it is always added to MAKEFLAGS. This allows a recursive make -n target to be used to see all of the action that would be taken to update target. Because of widespread historical practice, interpreting a # number sign inside a variable as the start of a comment has the unfortunate side effect of making it impossible to place a number sign in a variable, thus forbidding something like: CFLAGS = "-D COMMENT_CHAR='#'" Many historical make utilities stop chaining together inference rules when an intermediate target is non-existent. For example, it might be possible for a make to determine that both .y.c and .c.o could be used to convert a .y to a .o. Instead, in this case, make requires the use of a .y.o rule. The best way to provide portable makefiles is to include all of the rules needed in the makefile itself. The rules provided use only features provided by other parts of the standard. The default rules include rules for optional commands in the standard. Only rules pertaining to commands that are provided are needed in an implementation's default set. Macros used within other macros are evaluated when the new macro is used rather than when the new macro is defined. Therefore: MACRO = value1 NEW = $(MACRO) MACRO = value2 target: echo $(NEW) would produce value2 and not value1 since NEW was not expanded until it was needed in the echo command line. Some historical applications have been known to intermix target_name and macro=name operands on the command line, expecting that all of the macros will be processed before any of the targets are dealt with. Portable applications do not do this, although some backward compatibility support may be included in some implementations. The following characters in filenames may give trouble: = : ` ' @ For inference rules, the description of $< and $? seem similar. However, an example shows the minor difference. In a makefile containing: foo.o: foo.h if foo.h is newer than foo.o, yet foo.c is older than foo.o, the built-in rule to make foo.o from foo.c will be used, with $< equal to foo.c and $? equal to foo.h. If foo.c is also newer than foo.o, $< is equal to foo.c and $? is equal to foo.h foo.c. EXAMPLES 1. The following command: make makes the first target found in the makefile. 2. The following command: make junk makes the target junk. 3. The following makefile says that pgm depends on two files, a.o and b.o, and that they in turn depend on their corresponding source files (a.c and b.c), and a common file incl.h: pgm: a.o b.o c89 a.o b.o -o pgm a.o: incl.h a.c c89 -c a.c b.o: incl.h b.c c89 -c b.c 4. An example for making optimised .o files from .c files is: .c.o: c89 -c -O $*.c or: .c.o: c89 -c -O $< 5. The most common use of the archive interface follows. Here, it is assumed that the source files are all C-language source: lib: lib(file1.o) lib(file2.o) lib(file3.o) @echo lib is now up-to-date The .c.a rule is used to make file1.o, file2.o and file3.o and insert them into lib. The treatment of escaped newline characters throughout the makefile is historical practice. For example, the inference rule: .c.o\ : works, and the macro: f= bar baz\ biz a: echo ==$f== will echo ==bar baz biz==. If $? were: /usr/include/stdio.h /usr/include/unistd.h foo.h then $(?D) would be: /usr/include /usr/include . and $(?F) would be: stdio.h unistd.h foo.h 6. The contents of the built-in rules can be viewed by running: make -p -f /dev/null 2>/dev/null SEE ALSO ar, c89, cc, get, lex, sh, NOTES The VPATH facility is a derivation of the undocumented VPATH feature in the System V Release 3 version of make. System V Release 4 has a new VPATH implementation, much like the pmake(1) .PATH feature. This new feature is also undocumented in the standard System V Release 4 manual pages. For this reason it is not available in the IRIX version of make . The VPATH facility should not be used with the new parallel make option. An added feature is the ability for macros to be placed with macros. For example, when FLAGS = TYPE, then $(MAKE_${FLAGS}) will get expanded to the macro $(MAKE_TYPE). This syntax can handle about 100 levels of imbedding. COMPATIBILITY ISSUES When the special target .POSIX is not specified, the following backward compatible actions take place: 1. The content of the MAKEFLAGS variable will contain only the command line options and not command line macros. BUGS Filenames with the characters = : @ will not work. Commands that are directly executed by the shell, notably cd(1), are ineffectual across new-lines in make. The syntax (lib(file1.o file2.o file3.o) is illegal. You cannot build lib(file.o) from file.o. The macro $(a:.o=.c~) does not work. Named pipes are not handled well. Page 21